Session Type
Technical Talk
Date & Time
Wednesday, October 11, 2023, 11:00 AM - 11:30 AM
Vector codegen in the RISC-V backend

The RISC-V Vector extension (RVV) is a sizeable addition to the RISC-V architecture, and is quite different from the SIMD features of other targets in LLVM. This talk goes over some of the features unique to the vector-length agnostic RVV architecture, and how it compares to ARM's SVE. It also takes a look at the challenges they present, the infrastructure within LLVM to handle them, and how the auto-vectorization passes take advantage of RVV's modern design.

Location Name
Grand Ballroom