Date & Time
Monday, April 13, 2026, 11:00 AM - 11:30 AM
Name
Progressive Arithmetic Lowering to Synthesizable Datapaths
Session Type
MLIR Workshop
Abstract

This work presents an end-to-end MLIR-based compilation flow that lowers high-level machine-learning and DSP kernels to explicit combinational and sequential datapaths suitable for CIRCT and RTL export. The flow treats arithmetic as a multi-level concern, progressively exposing numeric intent, structured control, and hardware structure from tensor programs down to circuit-level IR. It integrates real-number expression recovery, configurable floating- and fixed-point lowering, and direct construction of circuit-level datapaths using CIRCT-compatible representations. The approach enables floating-point and specialized arithmetic to remain first-class up to the circuit boundary, supporting fine-grained trade-offs in precision, performance, and area. The flow has been validated on real silicon, including a taped-out DSP design using the GF180MCU open-source PDK and an end-to-end compilation of a PyTorch LLaMA layer into a synthesized Sky130 process-node.

Speakers: Louis Ledoux (INSA / INRIA Lyon), Pierre Cochard (INSA / INRIA Lyon), Florent de Dinechin (INSA / INRIA Lyon)

Location Name
Lansdowne