Date
Wednesday, October 28, 2026
Name
From Generic to Hardware-Aware Pipelines: Lessons from Retargeting an MLIR-Based End-to-End Compiler to a New NPU
Session Type
Technical Talk
Abstract
This talk presents lessons from retargeting an MLIR-based end-to-end ML compiler to the Hexagon NPU. It will be focused on the development process; starting from a CPU-based reference path and progressively introducing hardware-aware lowering. It will discuss examples involving memory management, vectorization, or runtime contracts to illustrate some of the engineering loops that emerged during the NPU bring-up.
Speakers
Location Name
Grand Ballroom