Hand-written kernels still dominate CPU convolution performance, while compiler-generated paths often lower convolution through im2col-style transformations to reuse matrix-multiplication infrastructure. This talk presents a direct, data-tiled Conv2D lowering path in MLIR/IREE that avoids im2col materialization and exposes the convolution reuse structure to MLIR's structured code-generation pipeline. We discuss how the tiled layout is derived from SIMD operand constraints, how the computation is represented and register-blocked using existing linalg abstractions, and how layout conversions between operations affect end-to-end performance. We then examine where this approach succeeds and where it falls short. The same lowering strategy that approaches XNNPACK performance on a wide, out-of-order x86 core remains well behind it on an in-order Arm (A55) core. Hardware counters, generated assembly, and code-generation experiments show that the gap is not simply a matter of scheduling the FMA chain. The talk uses these results to ask a broader question: not whether structured code generation can match hand-tuned kernels in principle, but what target information and representations are missing from the current stack and whether they belong in MLIR, in LLVM, or elsewhere.