The LPU (Language Processing Unit) is a tensor-streaming architecture deployed at production scale for AI inference, where data movement, placement, communication, and timing are controlled explicitly by software rather than hidden behind caches and dynamic scheduling. Compiling for this predictable execution model means the compiler has to resolve decisions that conventional machines defer to hardware and runtime systems. This talk dissects the production LPU compiler and shows how those constraints reshape familiar LLVM/MLIR problems. We trace tensor-level IR through layout, and multi-chip partitioning, SRAM allocation, and instruction level scheduling, looking at where each stage commits placement and timing and what must stay explicit for later stages to use. The output is a single distributed, cycle-accurate program across functional units, SRAM banks, streams, and chips. On this kind of hardware a value that arrives at the wrong place or the wrong cycle does not just slow the program down, it makes it wrong, and that is what makes the compiler central to the whole design.