LLVM’s scheduling model is a powerful framework that provides both performance data like instruction latency and micro-architectural level details useful for “hyper” hardware specific optimizations. It is one of the last frontiers for compiler engineers to unleash the full performance potential of target processors, especially as a record high number of new hardware architectures emerge every single day, all racing for peak performance. In this talk, we will provide an in depth tour into LLVM’s scheduling model framework. Started with a brief history of how LLVM’s scheduling model evolved over time, the talk puts majority of its attention on the principle and key design elements of the current scheduling model framework, with a specific focus on its connections with micro-architecture, instruction scheduler, other target-specific optimizations, and llvm-mca. All these lead to the final discussions on potential areas that can be improved in the future – making scheduling model engineering more ergonomic and increasing its adoption in target-specific optimizations within LLVM’s ecosystem, to name a few.