Date & Time
Monday, October 27, 2025, 1:30 PM - 5:30 PM
Name
LLVM ♥️ ML
Session Type
Workshop
Description
The workshop aims to bring together LLVM contributors and researchers that work on applying machine learning techniques to LLVM, including compiler optimizations, latency estimation, IR comprehension, code generation, or data set curation (to name a few) - to discuss their current, ongoing projects, and explore ways to better collaborate and plot pathways for integration into community LLVM.
Talk Order
<p>Yegor Denisov-Blanch: Does AI Boost Compiler Engineers’ Productivity?<br />
Jonas Devlieghere: AI & LLDB<br />
Yifan Zhang: ProfGen: LLM-Powered Generation of LLVM IR Benchmarks for Profile-Guided Optimization<br />
Jaden Angella: EmitC for MLGO<br />
Aiden Grossman: Large Scale Training for RL Guided Register Allocation<br />
Peter Rong: Careful What You Wish For - What we learned using MLGO for size optimization</p>
<p>– BREAK–</p>
<p>Hongzheng Chen: Magellan: Autonomous Discovery of Novel Compiler Optimization Heuristics with AlphaEvolve<br />
S. VenkataKeerthy: IR2Vec Embeddings: Lessons Learned and The Road Ahead<br />
Viraj Shah: **Towards Learning Latency Impact of Cache Misses: Retrofitting Learned BB Latency Models to Process LBR Traces”</p>
<p> </p>
Jonas Devlieghere: AI & LLDB<br />
Yifan Zhang: ProfGen: LLM-Powered Generation of LLVM IR Benchmarks for Profile-Guided Optimization<br />
Jaden Angella: EmitC for MLGO<br />
Aiden Grossman: Large Scale Training for RL Guided Register Allocation<br />
Peter Rong: Careful What You Wish For - What we learned using MLGO for size optimization</p>
<p>– BREAK–</p>
<p>Hongzheng Chen: Magellan: Autonomous Discovery of Novel Compiler Optimization Heuristics with AlphaEvolve<br />
S. VenkataKeerthy: IR2Vec Embeddings: Lessons Learned and The Road Ahead<br />
Viraj Shah: **Towards Learning Latency Impact of Cache Misses: Retrofitting Learned BB Latency Models to Process LBR Traces”</p>
<p> </p>
Location Name
Grand Ballroom Salons ABCD