We present a vector distribution framework for MLIR based on a customizable layout dataflow analysis, signature attributes, and a distribution pattern rewriter. This framework allows us to lower computation over n-D vector types to lower-level code tailored to the constraints of the target hardware like tensor cores or virtual ISAs like SPIR-V. Based on the experience with the implementation in the IREE compiler, we discuss possible future directions for moving parts of the work upstream to MLIR, and influencing the future direction of the MLIR vector abstractions.