Session Type
Technical Talk
Date & Time
Wednesday, April 10, 2024, 1:45 PM - 2:15 PM
Name
Leveraging LLVM Optimizations to Speed up Constraint Solving
Location Name
PSC I-III
Abstract/s
SLOT is a new tool which uses existing LLVM optimization passes to speed up SMT constraint solvers like Z3. While existing work has used SMT solving to verify LLVM’s peephole optimizations or in symbolic execution engines like KLEE, we flip the script and use LLVM optimizations to improve constraint solving. Our strategy is to translate SMT constraints into LLVM IR, apply the optimizer, and then translate back, alleviating manual developer effort in understanding both solver and LLVM internals. We find that SLOT speeds up average solving times by up to 2x for floating-point and bitvector constraints, and increases the number of constraints solved at fixed timeouts by up to 80%.
Speakers
Moderator
Javed Absar