Session Type
Technical Talk
Date & Time
Tuesday, May 10, 2022, 3:00 PM - 3:30 PM
Name
Hardware loops in the IPU backend
Speakers
Abstract/s
Albeit rare, more and more of today’s architectures implement their own concept of hardware loops; A set of instructions designed to aid the workhorse of computational algorithms: loops. Like these hardware loop enabled architectures, Graphcore’s IPU architecture has multiple of its own hardware loops. This talk will explore IPU’s hardware loops, their use, functionality, constraints, and lowering pipeline within LLVM.
Location Name
Ballroom 1