The following roundtables are scheduled, but please check the board outside the room for additional roundtables added during the event.
The idea of office hours is for people with some experience in LLVM to make themselves available for chats with others. The hope is that it will help overcome some of the biggest barriers to higher engagement in the community and barriers to start to contribute to LLVM.
We started office hours less than 1 year ago and already have about a dozen hosts, see https://llvm.org/docs/GettingInvolved.html#office-hours.
Let's discuss how we can further improve office hours, make their existence better-known and encourage more office hours hosts.
Loop Vectorizer Geared Towards RISC-V Vector Extension
Loop vectorizer is a critical component of modern compilers with its significance continuously growing in recent years. Advancement in AI/ML and a greater demand for computing power from new categories of performance critical applications are driving exciting hardware innovations in the vector processing space. RISC-V Vector Extension (RVV) is one such development in vector processor designs and brings a group of new features to this space; at the same time imposes a set of new challenges to the loop vectorizer.
This roundtable discusses how to evolve LLVM’s loop vectorizer to meet both the challenges and opportunities from RVV on topics such as the following.
Challenges and opportunities for the loop vectorizer targeting RVV
Path to converge on RVV vectorizer support in upstream
Should we base RVV loop vectorization on BSC VLA?
Should the loop vectorizer switch to vp-intrinsics for all targets? If not, do we want to abstract away code generation in the loop vectorizer?
RVV VLA vs ARM VLA
How to support RVV math functions?
How to support RVV scalarization?
Both experts and newcomers are welcome. Other topics are also welcome to be submitted before the conference for consideration.