Date & Time
Friday, November 19, 2021, 1:45 PM - 2:15 PM
Name
Bringing up GlobalISel for optimized AArch64 codegen
Description
The GlobalISel project aims to replace the backend instruction selection & optimization framework in LLVM with a new, more scalable architecture. It has been progressing over the past few years to go from an experimental prototype, to replacing FastISel at -O0 for AArch64, to now coming close to parity in performance and code size vs SelectionDAG. In this talk we'll cover this journey and how we arrived to the current state.
Speakers
Session Type
Technical Talk